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DGNA: Dissecting GPU NUMA Architecture through Microbenchmarking and Data Analysis

Changxi Liu, Yun Chen, Trevor E. Carlson 2026-07-24
Cache Coherence Memory Hierarchy Numa Microarchitecture Simulation HPC

The problem is that modern GPU memory architectures, particularly NUMA mechanisms within L2 and DRAM, remain black-boxes, hindering optimization and simulation. DGNA introduces a methodology using microbenchmarking and Gaussian mixture models to measure L2 and DRAM latency without relying on intrinsic instructions. Applied to NVIDIA A100 and H100 GPUs, it reveals NUMA node architecture, SM-NUMA relationships, and coherence-aware allocation strategies. This matters because it is the first work to detail GPU memory subsystem NUMA, enabling better application tuning and architectural design.

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DMG: A Scalable and Efficient Memory-Disaggregated Graph Processing System

Yizou Chen, Tsun-Yu Yang, Zhisheng Hu, Baotong Lu 2026-07-24
Data Architecture Cache Workload Runtime × Scheduling

Traditional graph processing systems on monolithic servers suffer from resource under-utilization, and existing disaggregated memory (DM) systems are impractical due to poor scalability and excessive compute-side cache demands. DMG introduces a DM-friendly graph store, an adaptive update coordinator, and a two-stage workload manager to address these issues. Experiments show DMG achieves up to 4.9X better performance and reduces cache demands by up to 18.9X compared to state-of-the-art DM-based systems. This matters because DMG is the first practical, scalable, and cache-efficient graph processing system for DM architectures, enabling efficient handling of growing graph sizes in data centers.

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