A Flexible Sparsity-Aware FPGA Accelerator with Column-Wise Compression for Efficient CNN Inference

The problem is that unstructured sparsity in CNNs causes hardware inefficiency, while structured sparsity sacrifices flexibility. SparHiXcel-v2, a flexible FPGA accelerator, uses a column-wise kernel compression technique and a scalable 2D MAC array to handle irregular sparsity with minimal overhead. On a cost-effective AMD Kintex UltraScale+ FPGA, it achieves over 2.5 TOPS and 210 GOP/s/W for VGG16 in structured sparsity mode with modest accuracy loss. This matters because it enables efficient CNN inference on resource-constrained platforms by balancing sparsity flexibility and hardware efficiency.