Investigating reservoir computing for branch predictionin pipelined processors using emerging CMOS memristor devices

The problem is that conventional branch predictors in pipelined processors struggle with adaptability and speed, motivating exploration of reservoir computing (RC) as an alternative. The method involves developing a novel memristor-based RC design framework, implemented in System Verilog and Verilog-AMS, and tested on the Dhrystone benchmark for the RISC-V RV64GC ISA. Experimental evidence shows that while the RC framework achieves impressive overall prediction accuracy, it is 15x slower to adapt to changes in branching behavior compared to the state-of-the-art TAGE predictor. This matters because RC shows promise for branch prediction but requires further refinement to overcome adaptability shortfalls before it can compete with existing predictors.