DGNA: Dissecting GPU NUMA Architecture through Microbenchmarking and Data Analysis

Changxi Liu, Yun Chen, Trevor E. Carlson 2026-07-26
Cache Coherence Memory Hierarchy Numa Microarchitecture Simulation HPC

The problem is that modern GPU memory architectures, particularly NUMA mechanisms within L2 and DRAM, remain black-boxes, hindering optimization and simulation. DGNA introduces a methodology using microbenchmarking and Gaussian mixture models to measure L2 and DRAM latency without intrinsic instructions. Applied to NVIDIA A100 and H100 GPUs, it reveals NUMA node architecture, SM-NUMA relationships, and NUMA-aware memory allocation strategies for cache coherence. This matters because it is the first detailed dissection of GPU memory subsystem NUMA, enabling better application optimization and architectural design.

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SLAI T-Rex: Full-Parameter Post-training of the DeepSeek-V4 Family on Ascend SuperPOD

Dongfang Li, Xiaodong Luo, Ruoyu Sun, Xuhui Chen 2026-07-26
LLM Training GPU Distributed

The problem is that full-parameter post-training of trillion-parameter-scale MoE models on Ascend NPU SuperPODs faces severe memory pressure, non-overlapped communication overhead, and inefficient kernel execution. The method is a hierarchical optimization framework spanning model-level parallelism, computation-communication orchestration, and low-level kernel execution, integrated as SLAI T-Rex, with a CPT and SFT workflow for Operations Research tasks. The system achieves 34.22% MFU with a 2.93x improvement over the baseline, and the specialized DeepSeek-V4-Flash model reaches 71.81% zero-shot Pass@1, outperforming GPT-5.4-Mini by 3.98 percentage points. This matters because it demonstrates a full-stack pathway from efficient trillion-parameter post-training on Ascend infrastructure to domain-specialized models for solver-grounded mathematical modeling, advancing frontier-model systems for complex reasoning.

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WaveformQA: Benchmarking LLM Temporal Reasoning on Digital Waveforms

Yichuan Liu, Daniel Cummings, Nick Vadlamudi 2026-07-26
Language Model LLM Hardware

The problem is that LLMs' ability to perform temporal reasoning over digital waveforms, a critical bottleneck in design verification, remains unexplored despite their strong code generation capabilities. The method introduces WaveformQA, an open-source benchmark with 360 programmatically grounded questions across eight difficulty categories, including multi-signal correlation and event ordering. Experimental evidence shows frontier LLMs achieve reasonable accuracy on simple queries but degrade on complex temporal and multi-step questions due to context window and reasoning limitations, with event-time JSON representation outperforming VCD format. This matters because WaveformQA provides a reproducible, extensible framework for evaluating and improving LLM temporal reasoning in real hardware verification tasks.

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PerfAgent: Profiler-Guided Iterative Refinement for Repository-Level Code Optimization

Ryan Deng, Yuanzhe Liu, Bastian Lipka, Yao Ma 2026-07-26
Language Model LLM Runtime

PerfAgent addresses the problem that LLM agents fail at repository-level code optimization because they miss hidden bottlenecks, stop after shallow speedups, and insufficiently test patches. The method is a profiler-guided, verifier-in-the-loop workflow that provides an off-the-shelf coding agent with feedback to find real hotspots and iteratively improve beyond the first passing patch. On GSO and SWE-fficiency-Lite, PerfAgent more than doubles the rate of expert-matching patches over OpenHands with GPT-5.1, improving from 19.6% to 39.2% and from 26% to 74%, respectively. This matters because it demonstrates that profiler-driven feedback, rather than additional test-time sampling, yields substantial and cost-effective optimization gains at the repository level.

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A Flexible Sparsity-Aware FPGA Accelerator with Column-Wise Compression for Efficient CNN Inference

Amirhossein Zarei, Shervin Vakili 2026-07-26
Microarchitecture Simulation Sparsity Accelerator Inference

The problem is that unstructured sparsity in CNNs causes hardware inefficiency, while structured sparsity sacrifices flexibility. SparHiXcel-v2, a flexible FPGA accelerator, uses a column-wise kernel compression technique and a scalable 2D MAC array to handle irregular sparsity with minimal overhead. On a cost-effective AMD Kintex UltraScale+ FPGA, it achieves over 2.5 TOPS and 210 GOP/s/W for VGG16 in structured sparsity mode with modest accuracy loss. This matters because it enables efficient CNN inference on resource-constrained platforms by balancing sparsity flexibility and hardware efficiency.

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A Reinforcement-Learning-Augmented Liquid-Fueled Reactor Network Model for Predicting Lean Blowout in Gas Turbine Combustors

Philip John, Eloghosa Ikponmwoba, Pinaki Pal, Opeoluwa Owoyele 2026-07-26
Design Space Exploration Agentic Architecture Network

The problem is that existing methods for determining reactor cluster boundaries in lean blowout (LBO) prediction rely on manual heuristics or distance-based metrics, which are not goal-oriented. The method introduces a reinforcement learning (RL) framework with a multi-stage clustering–classification strategy, using an actor-critic agent to merge micro-clusters into optimal reactor zones. Experimental evidence using a Jet-A mechanism shows the RL framework improves predictive fidelity over k-means, captures correct LBO trends, and achieves substantial speedups relative to high-fidelity models. This matters because the RL-driven approach offers a computationally efficient reduced-order modeling technique for rapid design-space exploration in gas turbine combustors.

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