Filtered by: GPU × Compiler × Runtime × Clear all

Optimizing CUDA like a Human: Micro-Profiling Tools as Expert Surrogates for LLM-Based GPU Kernel Optimization

Jiading Gai, Shuai Zhang, Kaj Bostrom, Jin Huang 2026-06-28
Triton CUDA Roofline Codesign Compiler × Runtime × HPC LLM

KernelPro addresses the challenge of automated GPU kernel optimization by introducing a closed-loop multi-agent system that integrates LLM code generation with hardware profiler feedback and pluggable micro-profiling tools. The method employs a two-stage tool invocation architecture with roofline-based bottleneck classification, domain-adapted MCTS search, and direct CuTe source-level code generation from the CUTLASS/CuTe codebase. On KernelBench, KernelPro achieves geometric mean speedups of 2.42x, 4.69x, and 5.30x on Levels 1, 2, and 3, and a 1.23x improvement over hand-tuned Triton on VeOmni's MoE kernels, with ablation studies confirming significant contributions from each design component. This matters because KernelPro is the first CUDA kernel coding agent to optimize energy efficiency beyond speed, achieving an 11.6% measured energy reduction at matched speed, establishing state-of-the-art performance across all difficulty levels.

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GPUSparse: GPU-Accelerated Learned Sparse Retrieval with Parallel Inverted Indices

Ashutosh Sharma 2026-06-28
Triton Codesign Compiler × Runtime × GPU × Sparsity

GPUSparse addresses the CPU bottleneck in learned sparse retrieval by introducing a GPU-accelerated inverted index with parallel scoring. The system uses block-aligned posting lists, batched scatter-add algorithms, and fused Triton kernels to process hundreds of queries simultaneously. On MS MARCO passage ranking, GPUSparse matches exact CPU scoring (MRR@10=0.383) while achieving a 235x speedup over Pyserini and 787 QPS throughput, unlike Seismic which sacrifices 25% recall for speed. This matters because it enables real-time, exact sparse retrieval at scale, revealing a fundamental work-efficiency versus bandwidth-efficiency tradeoff for GPU-based search systems.

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TileMaxSim: IO-Aware GPU MaxSim Scoring with Dimension Tiling and Fused Product Quantization

Ashutosh Sharma 2026-06-28
Triton Roofline Codesign Compiler × Runtime × HPC GPU ×

The problem is that existing GPU implementations of MaxSim scoring for multi-vector retrieval models achieve only 5-18% of peak HBM bandwidth due to materializing the full similarity matrix. The method, TileMaxSim, introduces IO-aware Triton kernels with multi-query SRAM tiling, dimension tiling for embeddings exceeding 128 dimensions, and fused product-quantization scoring via shared-memory lookup tables. On NVIDIA H100 GPUs, TileMaxSim reaches 80.2% of peak HBM bandwidth and scores 82M documents/second, achieving a 220x speedup over loop-based scoring and cutting ColBERTv2/PLAID scoring latency from 268 ms to 1.2 ms. This matters because it provides a drop-in replacement that preserves exact retrieval quality while dramatically reducing end-to-end latency and enabling efficient GPU utilization for state-of-the-art multi-vector retrieval models.

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