High-Performance NTT Accelerators for PQC leveraging Unified Redundant Arithmetic and Fine-Tuned Microarchitecture

The paper addresses the performance bottleneck of modular reduction and scaling overhead in NTT/INTT accelerators for lattice-based PQC schemes like ML-KEM and ML-DSA. The authors propose parallel iterative NTT/INTT accelerators using optimized unified butterfly units with a novel redundant number representation that eliminates conditional corrections and integrates inverse-transform scaling into existing hardware. FPGA-based experimental results demonstrate higher clock frequencies, reduced execution times, and competitive resource utilization compared to prior designs. This matters because it enables more efficient polynomial arithmetic for post-quantum cryptography and privacy-preserving applications, critical for future secure communication systems.