A Flexible Sparsity-Aware FPGA Accelerator with Column-Wise Compression for Efficient CNN Inference

SparHiXcel-v2 addresses the problem of balancing sparsity flexibility and hardware efficiency in CNN acceleration on resource-constrained platforms. The method introduces a column-wise kernel compression technique within a scalable two-dimensional MAC array and a hardware-algorithm co-design framework with ordering optimization and multi-phase structured pruning. Experimental results on VGG16 and ResNet18 show SparHiXcel-v2 achieves over 2.5 TOPS and 210 GOP/s/W for VGG16 on an AMD Kintex UltraScale+ FPGA with modest accuracy loss. This matters because it enables efficient, flexible sparsity-aware CNN inference on cost-effective FPGAs, improving throughput and energy efficiency for edge deployments.