Filtered by: Microarchitecture × Simulation × Clear all

Investigating reservoir computing for branch predictionin pipelined processors using emerging CMOS memristor devices

Harvey Samuel George Johnson, Sendy Phang 2026-07-31
Branch Prediction Physics App Ph Microarchitecture × Simulation ×

Problem: The paper investigates reservoir computing (RC) as a novel approach for branch prediction in pipelined processors, targeting high-speed operation and integration with CMOS digital logic using emerging memristor devices. Method: A memristor-based RC design framework was developed and implemented in simulation using System Verilog and Verilog-AMS, then verified with a sequence detection task and benchmarked for branch prediction on the RISC-V RV64GC ISA using the Dhrystone benchmark. Finding: Testing shows RC achieves impressive overall prediction accuracy for branch prediction, but it is 15x slower to adapt to changes in branching behavior compared to the state-of-the-art TAGE predictor, indicating shortfalls in adaptability. Why it matters: This work demonstrates RC's promise for branch prediction while highlighting the need for further refinement to compete with existing predictors, potentially enabling faster and more efficient processor designs.

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InferScale: GPU-Native KV Injection for Personalized LLM Serving

Peter Li, Prashant Pandey 2026-07-31
Memory Microarchitecture × Simulation × GPU Cache LLM Serving

InferScale is a GPU-native LLM memory system that replaces repeated prompt prefilling with reusable KV state, addressing the TTFT increase caused by injecting persistent personalized context into prompts. It precomputes KV representations for memory facts, stores them with semantic embeddings on the GPU, and injects them directly into vLLM's paged cache, using Chunked RoPE for dynamic memory assembly and Context-Window Encoding to mitigate the loss of cross-fact context. On LoCoMo with three open-weight models, InferScale keeps TTFT nearly constant as retrieval budget grows, reducing TTFT by 72-79% (3.6-4.8x) at k=50, achieving 60.3% accuracy versus 63.3% for Mem0, and delivering 3.7-4.5x throughput under concurrent load. This decouples memory-conditioned serving latency from retrieved-context size while preserving application quality, enabling efficient personalized LLM serving without engine modifications or fine-tuning.

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