Hardware Mechanisms to Dynamically Throttle AI Performance

The problem is the lack of fine-grained, dynamic hardware mechanisms to limit AI performance for safety, as existing software safeguards can be bypassed. The method introduces four microarchitecture knobs—L2 size, L2 latency, L2 bandwidth, and shared memory port access rate—built from established primitives like cache way masking and credit-based rate limiting. Experimental evidence shows these knobs achieve up to 80% performance reduction at 1/8 resource availability with negligible cost (<10K flip flops) and fast stabilization (5-80K cycles). This matters because it provides a hardware-level last line of defense for controlling AI intent in critical systems, with multi-knob combinations enabling a broader range of performance targets.