Filtered by: Cache × Microarchitecture × Clear all

Mapping Without Graphs: Learning Coherence Traffic for Task Placement

Guochu Xiong, Tianrui Ma, Weichen Liu 2026-07-22
Cache × Coherence Microarchitecture × Simulation

The problem is that existing task mapping approaches rely on predefined task graphs that fail to capture coherence-induced interactions from shared data accesses, leading to suboptimal mappings. CoTM addresses this by constructing task graphs inferred from dynamic coherence behavior and using a lightweight heuristic with a multi-start optimization strategy guided by a coherence-aware penalty function. Experimental results show CoTM reduces average link utilization by up to 47.85% and total energy consumption by up to 10.30% compared to existing approaches. This matters because it demonstrates that incorporating cache coherence into task mapping significantly improves performance and energy efficiency for future many-core NoC systems.

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Coherence in Control: Bridging Many-Core Mapping and Routing through Cost Unification

Guochu Xiong, Xiangzhong Luo, Weichen Liu 2026-07-22
Cache × Coherence Microarchitecture × Simulation

The problem is that existing many-core mapping and routing approaches overlook cache coherence, causing a mismatch between optimization objectives and actual communication patterns. CoCo proposes a unified cost model integrating communication cost, coherence overhead, and load imbalance to jointly optimize mapping and routing. Experiments show CoCo reduces link utilization by 88.46%, packet delay by 17.40%, and execution time by 17.58% over existing methods. This matters because it demonstrates that coherence-aware co-optimization is essential for improving performance in data-intensive many-core systems.

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Isolation Failure From Shared Storage: Characterizing and Exploiting Page-Cache SCA Leakage Across Containers and VMs

Alon Abudraham, Xingyu Chen, Itamar Levi, Ari Trachtenberg 2026-07-22
Microarchitecture × Microarchitectural Simulation Cache ×

The problem is that modern cloud platforms share the host page cache across containers and VMs, creating an OS-mediated microarchitectural timing side channel. The method involves unprivileged timing measurements to detect page-cache residency across Docker, gVisor, Kata Containers, and QEMU/KVM with various I/O paths. Experimental evidence shows the timing signal persists with shared host-cacheable file-backed objects like OverlayFS and virtio-fs, but direct I/O and dedicated block devices attenuate it; a case study recovers coarse-grained activity from a WordPress/MySQL deployment. This matters because it characterizes page-cache attacks as OS-mediated channels, motivating coordinated hardware, virtualization, and OS support for timing isolation.

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HyMCache: A KV Cache Framework for Multi-Turn LLM Serving with CXL-Hybrid Memory

Hakbeom Jang, Inho Song, Sam H. Noh, Jongryool Kim 2026-07-22
Prefetching Microarchitecture × Simulation Cache × LLM Serving

HyMCache addresses the problem of high memory costs in multi-turn LLM serving by proposing a KV-cache framework that uses CXL-hybrid memory (CXL-HM), combining a small in-device DRAM with large SSD-backed capacity. The method exploits the read-dominant, predictable, and append-only nature of multi-turn KV-cache access, using request-level prefix prefetching and opportunistic write buffering to stage latency-critical reads in device DRAM. Experimental evidence on a real CXL-HM prototype shows that under the same DRAM budget, HyMCache outperforms local LMCache by 3.0x in single-node serving and 1.45x in PD-disaggregated serving, and compared to 1 TB distributed-DRAM Mooncake, it incurs about 30% lower performance but uses 16x less DRAM. This matters because it enables TB-scale SSD-backed KV reuse at DRAM-scale efficiency and SSD-level cost, significantly reducing memory expenses for long-context and agentic LLM workloads.

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