Filtered by: Simulation × Clear all

Microflow: Microarchitectural Causal Observability for Deep Cross-Layer Analysis and Optimization

Saber Ganjisaffar, Chengyu Song, Nael Abu-Ghazaleh 2026-07-19
Microarchitectural Microarchitecture Simulation ×

The problem is that existing architectural simulators expose aggregate metrics or raw traces but fail to reveal complex interactions among microarchitectural events and their relationship to program execution. Microflow introduces an observability framework that transforms execution traces into the Microflow Intermediate Representation (MFIR), explicitly capturing dependencies across software semantics, instructions, microarchitectural events, and hardware resources. On two SPEC CPU 2017 benchmarks, Microflow uncovers bottlenecks invisible from aggregate symptoms, such as hidden misprediction costs in leela and cross-loop-iteration contention in mcf. This matters because making causality queryable provides a strong foundation for performance analysis and hardware-software co-design, enabling systematic reasoning about complex interactions opaque to existing tools.

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ExaGEMM: Exploration Framework for CPU-Driven ML Inference via Associative In-Register Computing for Low-Bit GEMM

Hyunwoo Oh, Suyeon Jang, Hanning Chen, Sanggeon Yun 2026-07-19
Gem5 Microarchitecture Simulation × Inference

The problem is that low-bit GEMM is central to efficient ML inference, but very-low-bit execution is poorly suited for conventional CPUs, and fragmented precision regimes make lightweight CPU support selection a first-class design challenge. ExaGEMM proposes a workload-aware codesign framework for CPU-native low-bit GEMM via register-resident LUT execution, requiring only an in-register select/feed mechanism with explicitly modeled cost. Experimental evidence shows ExaGEMM improves latency by 13.29x over software-only baselines across representative ML models and CPU targets, while pruning the candidate space by 99.2% before simulation. This matters because it demonstrates that workload-aware frontier selection is especially important for mixed-precision LLM workloads, enabling efficient CPU-driven ML inference without major hardware redesign.

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Valinor: Architectural Support for Fast, Energy-Efficient and Programmable Physical Memory Allocation

Konstantinos Kanellopoulos, Spiros Galanopoulos, Konstantinos Sgouras, Vlad-Petru Nitu 2026-07-19
Workload Runtime Hardware Simulation ×

The problem is that physical memory allocation in current systems incurs high overhead from minor page faults, which can account for up to 54% of runtime and 40% of system energy in short-lived workloads like serverless functions. The method, Valinor, is a hardware-OS cooperative substrate that introduces a programmable hardware allocation engine executing compact OS-supplied allocation libraries at near fixed-hardware speed. On a BOOM RISC-V soft core running Linux, Valinor accelerates allocation by 17x, improves end-to-end performance by 16%, and reduces energy consumption by up to 8%, with full-system simulation confirming hardware-class performance across six allocation libraries. This matters because Valinor provides the flexibility to support diverse allocation policies and adapt to new hardware conditions while achieving the performance and energy efficiency of dedicated hardware.

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