A Flexible Sparsity-Aware FPGA Accelerator with Column-Wise Compression for Efficient CNN Inference

Problem: Efficient CNN inference on resource-constrained FPGAs is challenged by the irregularity of sparsity patterns, where unstructured sparsity causes hardware inefficiencies and structured sparsity sacrifices flexibility. Method: SparHiXcel-v2 introduces a scalable two-dimensional MAC array with column-wise kernel compression for irregular sparsity, plus a hardware-algorithm co-design framework with ordering optimization and multi-phase structured pruning and revival. Finding: On a cost-effective AMD Kintex UltraScale+ FPGA, SparHiXcel-v2 achieves over 2.5 TOPS and 210 GOP/s/W for VGG16, and over 1.1 TOPS and 72 GOP/s/W for ResNet18 in structured sparsity mode with modest accuracy loss. Why it matters: This work provides a flexible, energy-efficient FPGA accelerator that balances sparsity flexibility and hardware efficiency, enabling practical CNN deployment on resource-constrained platforms.