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SEAM-V: A Hybrid-Decoupled RISC-V Vector Processor with Backend-Visible EP Context for Sustained Vector Throughput

Weiying Wang, Zhiwei Zhang 2026-07-22
Prefetching × Microarchitecture Simulation ×

SEAM-V addresses the problem of vector-instruction supply gaps and scalar-side progression delays in tightly coupled RISC-V Vector Extension implementations. The method introduces a hybrid-decoupled architecture that forms continuous execute packets via task-level decoupling, local instruction supply, and VLIW-style packing, with backend-visible EP context for hazard suppression and prefetching. Cycle-accurate RTL evaluation shows a geometric-mean speedup of 1.34x across 17 kernels compared to an Ara-based tightly coupled implementation, with up to 3x speedup for short-vector kernels at AVL=32. This matters because it demonstrates a scalable approach to sustaining vector throughput in data-parallel workloads without relying solely on scalar core progression.

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HyMCache: A KV Cache Framework for Multi-Turn LLM Serving with CXL-Hybrid Memory

Hakbeom Jang, Inho Song, Sam H. Noh, Jongryool Kim 2026-07-22
Prefetching × Microarchitecture Simulation × Cache LLM Serving

HyMCache addresses the problem of high memory costs in multi-turn LLM serving by proposing a KV-cache framework that uses CXL-hybrid memory (CXL-HM), combining a small in-device DRAM with large SSD-backed capacity. The method exploits the read-dominant, predictable, and append-only nature of multi-turn KV-cache access, using request-level prefix prefetching and opportunistic write buffering to stage latency-critical reads in device DRAM. Experimental evidence on a real CXL-HM prototype shows that under the same DRAM budget, HyMCache outperforms local LMCache by 3.0x in single-node serving and 1.45x in PD-disaggregated serving, and compared to 1 TB distributed-DRAM Mooncake, it incurs about 30% lower performance but uses 16x less DRAM. This matters because it enables TB-scale SSD-backed KV reuse at DRAM-scale efficiency and SSD-level cost, significantly reducing memory expenses for long-context and agentic LLM workloads.

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