Ramulator 2.1: A Composable Memory System Simulator for Modern DRAM Systems

Ramulator 2.1 addresses the problem of simulating modern DRAM systems with limited support for emerging standards and poor usability. The method introduces a Python-based modeling interface with two-way code generation, hiding C++ complexity while enabling rapid DRAM variant creation and automated design-space exploration. Experimental evidence shows comprehensive validation through fine-grained DRAM timing checks and system-level latency-throughput curves, alongside a high-performance command trace visualizer. This matters because it provides an open-source, extensible, and trustworthy simulation framework for researchers to evaluate and innovate on HBM3/4, LPDDR5/6, GDDR7, and future memory systems.