Ramulator 2.1: A Composable Memory System Simulator for Modern DRAM Systems

Ramulator 2.1 addresses the problem of simulating modern DRAM systems with limited support for emerging standards and poor usability. The method introduces a Python-based modeling interface with two-way code generation, hiding C++ complexity and enabling rapid DRAM variant creation. Experimental evidence shows comprehensive validation through fine-grained timing constraint checks and system-level latency-throughput curves, though the abstract does not disclose specific performance numbers. This matters because it provides an open-source, extensible, and trustworthy simulator for researchers to explore HBM3/4, LPDDR5/6, and GDDR7 memory systems.